Resumen

BOLANOS, FREDDY  y  BERNAL, ÁLVARO. A HARDWARE OPTIMIZED IMPLEMENTATION FOR THE MODULAR EXPONENTIATION OPERATOR. Dyna rev.fac.nac.minas [online]. 2008, vol.75, n.156, pp.55-63. ISSN 0012-7353.

This paper shows the optimization of the Modular Exponentiation operator, taking advantage of design tools such as the VHDL language and FPGA devices. Since the implementation occurs in a hardware-limited environment, the cost function used regarding optimization purposes includes both the execution time of the operator and the area occupied by the design. Three alternatives for the Modular Exponentiation operator have been considered. These alternatives are then compared in terms of their associated cost functions. Finally, the feasibility of the implementation of such alternatives in specific environments is discussed.

Palabras clave : Cryptography; Modular Arithmetic; VHDL; FPGA.

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