Abstract

GUZMAN, Ian Carlo; NIETO, Rubén Darío  and  BERNAL, Álvaro. FPGA implementation of the AES-128 algorithm in non-feedback modes of operation. Dyna rev.fac.nac.minas [online]. 2016, vol.83, n.198, pp.37-43. ISSN 0012-7353.  https://doi.org/10.15446/dyna.v83n198.55251.

In this paper, we present a hardware implementation of the pipelined AES-128 algorithm that works on non-feedback modes of operation (ECB and CTR). The architecture was implemented using the Xilinx Virtex 5 FPGA platform. We compared two modes of operation (ECB, CTR) for encryption and decryption according to device utilization, throughput, and security. A clock frequency of 272.59Mhz for the ECB encryption process was obtained, which is equivalent to a throughput of 34.89 Gb/s. Also, we obtained a clock frequency of 199.48Mhz for the decryption process, which is equivalent to a throughput of 25.5Gb/s. In CTR mode, we obtained a clock frequency of 272.59Mhz, which is equivalent to a throughput of 34.89Gb/s.

Keywords : AES; G; ECB; CTR; Pipelined; Throughput.

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