Resumen

ARENAS-HOYOS, Sergio Andrés  y  BERNAL-NORENA, Álvaro. Performance evaluation of M-ary algorithm using reprogrammable hardware. Dyna rev.fac.nac.minas [online]. 2017, vol.84, n.203, pp.75-79. ISSN 0012-7353.  https://doi.org/10.15446/dyna.v84n203.65480.

Several ways to perform data encryption have been found, and one of the functions involved in standard algorithms such as RSA is the modular exponentiation. Basically, the RSA algorithm uses some properties of modular arithmetic to cipher and decipher plain text, with a certain performance dependence on text lengths. The growth in computing capacity has created the need to use robust systems that can perform calculations with significantly large numbers and the formulation of procedures focused on improving the speed to achieve it. One of these is the M-ary algorithm for the execution of the modular exponential function. This paper describes an implementation of this algorithm in reprogrammable hardware (FPGA) to evaluate its performance.

The first section of this work introduces the M-ary algorithm. The second section uses block description for implementation understanding. The third section shows the results in time diagrams, and finally, the last section conclusions.

Palabras clave : cryptosystems; modular exponentiation; modular arithmetic; RSA algorithm; FPGA; M-ary algorithm..

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