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Ingeniería e Investigación

Print version ISSN 0120-5609

Abstract

IENO, E; GARCES, L.M; CABRERA, A.J  and  PIMENTA, T.C. Simple generation of threshold for images binarization on FPGA. Ing. Investig. [online]. 2015, vol.35, n.3, pp.69-75. ISSN 0120-5609.  http://dx.doi.org/10.15446/ing.investig.v35n3.51750.

The methodologies presented in scientific literature to calculate the threshold of an image binarization process do not present good results for all types of images. Additionally, the hardware implementations do not consider the FPGA resources that are used in other processing phases. Thus, the method proposed in this work aims to present good results in the binarization process with under-resourced area of FPGA. Therefore, this paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation only needs one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu's method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by a model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in cosimulation system and show the effectiveness of the proposed method.

Keywords : Digital image processing; threshold; FPGA; System Generator®; Matlab®/Simulink®.

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