Abstract

RIOS-COTA, Norma X.  and  BERNAL-NORENA, Álvaro. Hardware Architecture for the Implementation of the Discrete Wavelet Transform in two Dimensions. Ing. compet. [online]. 2014, vol.16, n.1, pp.69-81. ISSN 0123-3033.

This paper presents a hardware architecture developed by the two-dimensional wavelet transform on an FPGA, in the design it was searched a balance between the number of required logic cells and the processing speed. The design is based on a methodology to reuse the input data with a parallel-pipelined structure and a calculation of the coefficients is performed using a method of odd and even numbers, which is achieved by calculating a cycle ratio after 2 cycles latency, to store the data processing result of the SDRAM memory is used IS42S16400, the control unit uses a design architecture supported by Nios II processor. The system was implemented in the FPGA Altera Cyclone II EP2C35F672C6 using a design that combines descriptions in VHDL, schematics and control connection via a general purpose processor

Keywords : Hardware Architectures; FPGA; Nios Processor; Wavelet transform.

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