<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1794-1237</journal-id>
<journal-title><![CDATA[Revista EIA]]></journal-title>
<abbrev-journal-title><![CDATA[Rev.EIA.Esc.Ing.Antioq]]></abbrev-journal-title>
<issn>1794-1237</issn>
<publisher>
<publisher-name><![CDATA[Escuela de ingenieria de Antioquia]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1794-12372012000100013</article-id>
<title-group>
<article-title xml:lang="es"><![CDATA[DISEÑO DE UN AMPLIFICADOR RIEL A RIEL CON TECNOLOGÍA CMOS 0,18 µm]]></article-title>
<article-title xml:lang="en"><![CDATA[DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY]]></article-title>
<article-title xml:lang="pt"><![CDATA[DESENHO DE UM AMPLIFICADOR DO TRILHO-A-TRILHO COM TECNOLOGIA CMOS 0,18 µm]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Hernández]]></surname>
<given-names><![CDATA[Diego F.]]></given-names>
</name>
<xref ref-type="aff" rid="A01"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Antolínez]]></surname>
<given-names><![CDATA[Juan F.]]></given-names>
</name>
<xref ref-type="aff" rid="A02"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Pineda]]></surname>
<given-names><![CDATA[Elkin Y.]]></given-names>
</name>
<xref ref-type="aff" rid="A03"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Yamhure]]></surname>
<given-names><![CDATA[Germán]]></given-names>
</name>
<xref ref-type="aff" rid="A04"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[Páez]]></surname>
<given-names><![CDATA[Carlos Iván]]></given-names>
</name>
<xref ref-type="aff" rid="A05"/>
</contrib>
</contrib-group>
<aff id="A01">
<institution><![CDATA[,Pontificia Universidad Javeriana  ]]></institution>
<addr-line><![CDATA[Bogotá ]]></addr-line>
<country>Colombia</country>
</aff>
<aff id="A02">
<institution><![CDATA[,Pontificia Universidad Javeriana  ]]></institution>
<addr-line><![CDATA[Bogotá ]]></addr-line>
<country>Colombia</country>
</aff>
<aff id="A03">
<institution><![CDATA[,Pontificia Universidad Javeriana  ]]></institution>
<addr-line><![CDATA[Bogotá ]]></addr-line>
<country>Colombia</country>
</aff>
<aff id="A04">
<institution><![CDATA[,Pontificia Universidad Javeriana Departamento de Electrónica Grupo de investigación en Telecomunicaciones (SISCOM)]]></institution>
<addr-line><![CDATA[Bogotá ]]></addr-line>
<country>Colombia</country>
</aff>
<aff id="A05">
<institution><![CDATA[,Pontificia Universidad Javeriana Departamento de Electrónica ]]></institution>
<addr-line><![CDATA[Bogotá ]]></addr-line>
<country>Colombia</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>06</month>
<year>2012</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>06</month>
<year>2012</year>
</pub-date>
<numero>17</numero>
<fpage>167</fpage>
<lpage>181</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_arttext&amp;pid=S1794-12372012000100013&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_abstract&amp;pid=S1794-12372012000100013&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_pdf&amp;pid=S1794-12372012000100013&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="es"><p><![CDATA[En este artículo se realiza el análisis, diseño y simulación de un amplificador rail to rail R-R (riel a riel) a la entrada y a la salida utilizando una fuente sencilla de 3,3 V. La tecnología usada fue CMOS TSMC de 0,18 µm, de bajo costo relativo para uso académico. El proceso de implementación se hizo con herramientas industrial Synopsys. En el artículo se detalla la etapa de entrada R-R complementaria, se describen el circuito sumador y la etapa de salida R-R clase AB. Finalmente, se muestran el layout definitivo y los resultados de la evaluación del diseño.]]></p></abstract>
<abstract abstract-type="short" xml:lang="en"><p><![CDATA[This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18µm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.]]></p></abstract>
<abstract abstract-type="short" xml:lang="pt"><p><![CDATA[Em este artigo realiza-se a análise, desenho e simulação de um amplificador rail to rail R-R (trilho a trilho) à entrada e à saída utilizando uma fonte singela de 3,3 V. A tecnologia usada foi CMOS TSMC de 0,18 µm, de relativo baixo custo para uso acadêmico. O processo de implementação realizou-se com ferramentas industrial Synopsys. No artigo detalha-se a etapa de entrada R-R complementar, descreve-se o circuito somador e a etapa de saída R-R classe AB. Finalmente, mostra-se o layout definitivo e os resultados da avaliação do desenho.]]></p></abstract>
<kwd-group>
<kwd lng="es"><![CDATA[VLSI]]></kwd>
<kwd lng="es"><![CDATA[amplificador carril a carril]]></kwd>
<kwd lng="es"><![CDATA[CMOS]]></kwd>
<kwd lng="es"><![CDATA[layout]]></kwd>
<kwd lng="en"><![CDATA[VLSI]]></kwd>
<kwd lng="en"><![CDATA[rail to rail operational amplifier]]></kwd>
<kwd lng="en"><![CDATA[CMOS]]></kwd>
<kwd lng="pt"><![CDATA[VLSI]]></kwd>
<kwd lng="pt"><![CDATA[amplificador operacional trilho a trilho]]></kwd>
<kwd lng="pt"><![CDATA[CMOS]]></kwd>
</kwd-group>
</article-meta>
</front><body><![CDATA[  ]]></body><back>
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