<?xml version="1.0" encoding="ISO-8859-1"?><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<front>
<journal-meta>
<journal-id>1794-1237</journal-id>
<journal-title><![CDATA[Revista EIA]]></journal-title>
<abbrev-journal-title><![CDATA[Rev.EIA.Esc.Ing.Antioq]]></abbrev-journal-title>
<issn>1794-1237</issn>
<publisher>
<publisher-name><![CDATA[Escuela de ingenieria de Antioquia]]></publisher-name>
</publisher>
</journal-meta>
<article-meta>
<article-id>S1794-12372020000100194</article-id>
<article-id pub-id-type="doi">10.24050/reia.v17i33.1318</article-id>
<title-group>
<article-title xml:lang="en"><![CDATA[Parametric Decimal Division using Hardware Description Language]]></article-title>
<article-title xml:lang="es"><![CDATA[División Decimal Parametrizable usando Lenguaje de Descripción de Hardware]]></article-title>
<article-title xml:lang="pt"><![CDATA[Divisão decimal paramétrica usando a linguagem de descrição de hardware]]></article-title>
</title-group>
<contrib-group>
<contrib contrib-type="author">
<name>
<surname><![CDATA[LÓPEZ]]></surname>
<given-names><![CDATA[JORGE HERNÁN]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[RESTREPO]]></surname>
<given-names><![CDATA[JOHANS]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
<contrib contrib-type="author">
<name>
<surname><![CDATA[TOBÓN]]></surname>
<given-names><![CDATA[JORGE E.]]></given-names>
</name>
<xref ref-type="aff" rid="Aff"/>
</contrib>
</contrib-group>
<aff id="Af1">
<institution><![CDATA[,Universidad de Antioquia Instituto de Física ]]></institution>
<addr-line><![CDATA[Medellín ]]></addr-line>
<country>Colombia</country>
</aff>
<pub-date pub-type="pub">
<day>00</day>
<month>06</month>
<year>2020</year>
</pub-date>
<pub-date pub-type="epub">
<day>00</day>
<month>06</month>
<year>2020</year>
</pub-date>
<volume>17</volume>
<numero>33</numero>
<fpage>194</fpage>
<lpage>199</lpage>
<copyright-statement/>
<copyright-year/>
<self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_arttext&amp;pid=S1794-12372020000100194&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_abstract&amp;pid=S1794-12372020000100194&amp;lng=en&amp;nrm=iso"></self-uri><self-uri xlink:href="http://www.scielo.org.co/scielo.php?script=sci_pdf&amp;pid=S1794-12372020000100194&amp;lng=en&amp;nrm=iso"></self-uri><abstract abstract-type="short" xml:lang="en"><p><![CDATA[ABSTRACT In this work we describe a fast and high-precision algorithm written in VHDL Hardware Description Language to perform the division between two_nite decimal numbers, i.e. numbers composed of an integer part and a decimal one, under the scheme of a fixed point representation. The algorithm proposed is not an approximation one as it is usually considered. To do so, the size of the bits of the operands can be tunned by means of a couple of parameters N and M, according to which the latency of the calculation will depend. The project is finally sinthesized in a _eld programmable gate array or FPGA of the type SPARTAN 3E from XILINX.]]></p></abstract>
<abstract abstract-type="short" xml:lang="es"><p><![CDATA[RESUMEN En este trabajo se describe un algoritmo rápido y de alta precisión escrito en el lenguaje de descripción de hardware, VHDL para realizar la división entre dos números decimales, es decir, los números compuestos por una parte entera y una decimal, bajo el esquema de una representación de punto fijo. El algoritmo propuesto no es una aproximación, como se hace en la mayoría de los casos, escogiendo el algoritmo según la necesidad propia, en tiempo o en área de lógica. Para ello, el tamaño de los bits de los operandos se puede ajustar mediante un par de parámetros N y M, según los cuales dependerá la latencia del cálculo. El proyecto se sintetiza finalmente en una matriz de puertas programables o FPGA del tipo SPARTAN 3E de XILINX.]]></p></abstract>
<abstract abstract-type="short" xml:lang="pt"><p><![CDATA[RESUMO Neste trabalho descrevemos um algoritmo rápido e de alta precisão escrito na linguagem de descrição de hardware, VHDL, para realizar a divisão entre dois números decimais, ou seja, os números compostos por uma parte inteira e uma parte decimal, sob o esquema de uma representação de ponto fixo. O algoritmo proposto não é uma aproximação, como é feito na maioria dos casos, escolhendo o algoritmo de acordo com a própria necessidade, no tempo ou na área lógica. Para isso, o tamanho dos bits do operando pode ser ajustado por um par de parâmetros N e M, dependendo de qual dependerá a latência do cálculo. O projeto é finalmente sintetizado em uma matriz de portas programáveis ou FPGA do tipo SPARTAN 3E da XILINX.]]></p></abstract>
<kwd-group>
<kwd lng="en"><![CDATA[VHDL]]></kwd>
<kwd lng="en"><![CDATA[FPGA]]></kwd>
<kwd lng="en"><![CDATA[OPERATION]]></kwd>
<kwd lng="en"><![CDATA[DIVISION]]></kwd>
<kwd lng="es"><![CDATA[Palabras cables: VHDL]]></kwd>
<kwd lng="es"><![CDATA[FPGA]]></kwd>
<kwd lng="es"><![CDATA[OPERACIÓN]]></kwd>
<kwd lng="es"><![CDATA[DIVISIÓN]]></kwd>
<kwd lng="pt"><![CDATA[VHDL]]></kwd>
<kwd lng="pt"><![CDATA[FPGA]]></kwd>
<kwd lng="pt"><![CDATA[OPERAÇÃO]]></kwd>
<kwd lng="pt"><![CDATA[DIVISÃO]]></kwd>
</kwd-group>
</article-meta>
</front><back>
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