Resumen

GONZALEZ, Edwin; VILLAMIZAR LUNA, Walter D.  y  FAJARDO ARIZA, Carlos Augusto. A Hardware Accelerator for The Inference of a Convolutional Neural Network. Cienc. Ing. Neogranad. [online]. 2020, vol.30, n.1, pp.107-116.  Epub 16-Ago-2020. ISSN 0124-8170.  https://doi.org/10.18359/rcin.4194.

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, CNN inference is computationally intensive and demands a large number of memory resources. This work proposes a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce hardware resources and achieve the best possible throughput. The design is implemented in the Digilent Arty Z7-20 development board, which is based on the Xilinx Zynq-7000 System on Chip (SoC). Our implementation achieved a of accuracy for the MNIST database using only a 12-bits fixed-point format. Results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other Field-Programmable Gate Array (FPGA)-based implementations because they are not exactly like ours. However, some comparisons, regarding logical resources used and accuracy, suggest that our work could be better than previous ones. Besides, the proposed scheme is compared with a hardware implementation in terms of power consumption and throughput.

Palabras clave : CNN; FPGA; hardware accelerator; MNIST; Zynq.

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